The invention relates to MOS voltage divider circuits and particularly to an improved voltage divider in which threshold voltage and ambient temperature variations have little influence on the output voltage.
MOS voltage dividers are in wide use, for instance as reference voltage generators for the differential amplifier type input buffers on 4K and 16K dynamic RAMS (random access memories). The term MOS is shortened from the abbreviation MOSFET, which means metal oxide semiconductor field effect transistor. Generally, these voltage generators require many transistors in series, thereby causing many threshold voltage drops, which in turn is acceptable only with relatively high input voltages.
U.S. Pat. No. 4,069,430 to Masuda, issued Jan. 17, 1978, discloses a MOS voltage divider circuit having both enhancement and depletion type transistors all connected in series. German patent application No. 2,435,606 published June 22, 1968, discloses two depletion type transistors connected in series. U.S. Pat. No. 4,152,716 to Torii et al, issued May 1, 1979, discloses a plurality of enhancement type transistors all connected in series.